Design and optimize multi-layer PCB stackups for controlled impedance.
| Visual | Layer Name | Type | Material | Thickness | Dk | Df | Cu Weight | |
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| Total Stack | 101.9 mil | (2.59 mm) | ||||||
Keep the stackup symmetric about the center to prevent warpage during fabrication.
Every signal layer should have an adjacent ground or power plane for return current.
Route high-speed signals on layers adjacent to GND planes, not power planes.
Balance copper distribution on each side to prevent bow and twist.
Master the art of multi-layer PCB stackup design for optimal signal integrity and manufacturability.
| Style | Thickness | Resin % | Use |
|---|---|---|---|
| 1080 | 2.8 mil | 65% | Thin stackups |
| 2116 | 4.5 mil | 52% | Most common |
| 1506 | 5.5 mil | 48% | Medium |
| 7628 | 7.0 mil | 42% | Thick builds |
| Thickness (mil) | mm | Common Use |
|---|---|---|
| 4 | 0.1 | HDI, thin boards |
| 8 | 0.2 | High-layer count |
| 20 | 0.5 | Standard 6+ layer |
| 40 | 1.0 | 4-layer standard |
| 60 | 1.5 | Thick 2-layer |
Always design stackups symmetric about the center. Asymmetric stackups cause warpage during reflow, leading to assembly defects.
Every signal layer should have an adjacent GND or PWR plane. This provides a low-inductance return path for high-speed signals.
Prefer GND planes as reference for high-speed signals. Power planes have higher noise due to switching currents.
Each via adds inductance and causes impedance discontinuity. Route critical signals on a single layer when possible.
Inner layers etch differently than outer layers. Work with your fab to understand their etch factors for accurate impedance.
At high speeds (10G+), Dk varies with trace orientation vs glass weave. Use spread glass or rotate traces 7-15°.