What is a Via?
A via (Vertical Interconnect Access) is a plated hole in a PCB that creates electrical connections between different copper layers. Vias are essential for routing signals and power through multi-layer boards, but they introduce parasitic effects that can degradesignal integrityat high frequencies.
Key Insight
At frequencies above 1 GHz, a via is no longer just a simple connection—it becomes atransmission linediscontinuity with its own impedance, inductance, and capacitance. Understanding these parasitic effects is crucial for modern high-speed design including USB 3.x,PCIe, and10G+ Ethernet.
A typical via consists of several components:
- Barrel: The plated cylinder through the board
- Pad: The copper area around the hole on each layer
- Annular ring: The copper ring between hole and pad edge
- Anti-pad: The clearance hole in plane layers
Via Types Explained
Choosing the right via type is crucial for balancing cost, manufacturability, and performance. Here's a detailed comparison of each type and when to use them:
Through-Hole Via (PTH)
Connects all layers from top to bottom. Most common and economical type.
Advantages
- Lowest cost
- Simple manufacturing
- High reliability
Disadvantages
- Creates stub on signal layers
- Uses routing space on all layers
- Not suitable for high-density
Best For
General routing, power distribution, low-speed signals
Blind Via
Connects outer layer to one or more inner layers, but not through entire board.
Advantages
- No stub on opposite side
- Better for high-speed
- Saves routing space
Disadvantages
- Higher cost
- More complex manufacturing
- Requires sequential lamination
Best For
High-speed signals, HDI boards, space-constrained designs
Buried Via
Connects inner layers only, invisible from both surfaces.
Advantages
- Maximum routing density
- No surface impact
- Excellent for HDI
Disadvantages
- Highest cost
- Complex manufacturing
- Limited repairability
Best For
HDI designs, mobile devices, high-layer-count boards
Microvia
Small laser-drilled via (≤150µm) connecting adjacent layers.
Advantages
- Minimal parasitic effects
- Highest density
- Best for high-speed
Disadvantages
- Limited aspect ratio
- Requires laser drilling
- Cost per via higher
Best For
BGA fanout, smartphone PCBs, advanced packaging
Industry Standards Reference
Via design requirements are defined in IPC standards:
Via Parameters & Specifications
| Parameter | Standard | High-Speed | HDI/Microvia |
|---|---|---|---|
| Drill Diameter | 10-12 mils | 8-10 mils | 4-6 mils |
| Pad Diameter | 20-24 mils | 16-20 mils | 10-14 mils |
| Annular Ring | 5-6 mils | 4-5 mils | 3-4 mils |
| Anti-pad | 30-40 mils | 25-30 mils | 15-20 mils |
| Aspect Ratio | 8:1 | 10:1 | 0.75:1 - 1:1 |
Aspect ratio is the board thickness divided by drill diameter. Higher aspect ratios are harder to plate reliably. For a 62-mil board with 8-mil drill, aspect ratio = 62/8 = 7.75:1.
Manufacturing Tip
Always consult your PCB fabricator's capabilities before finalizing via specifications. Standard fabs typically support 10:1 aspect ratio, while advanced fabs can achieve 15:1 or higher. Using capabilities beyond your fab's limits leads to reliability issues or outright rejection.
Via Impedance & Signal Integrity
A via has its own characteristic impedance, typically 25-35Ω for standard geometries—much lower than the typical 50Ω trace. This impedance mismatch causes reflections that can degrade high-speed signals.
// Via Impedance Approximation
Z_via ≈ (60 / √εr) × ln(D_antipad / D_via)
// Via Inductance
L_via ≈ 5.08 × h × (ln(4h/d) + 1) nH
// Via Capacitance
C_via ≈ 1.41 × εr × h × D_pad / (D_antipad - D_pad) pF
See our complete formula reference for detailed derivations and examples.
Reducing Via Discontinuity
Increase Via Impedance
- • Use smaller via diameter
- • Increase anti-pad size
- • Reduce pad size (within limits)
- • Use non-functional pads (NPTH)
Provide Return Path
- • Add ground vias nearby
- • Stitch ground planes at layer transitions
- • Minimize via stub length
- • Consider back-drilling
Back-Drilling Techniques
Back-drilling (also called controlled-depth drilling) removes the unused portion of a via barrel to eliminate the stub that causes signal resonance and reflection at high frequencies.
Via Stub Resonance Reference
| Stub Length | Resonance (FR-4) | Impact |
|---|---|---|
| 50 mil | ~30 GHz | Minor for <10 Gbps |
| 100 mil | ~15 GHz | Affects 25G+ signals |
| 150 mil | ~10 GHz | Critical for 10G+ |
| 200 mil | ~7.5 GHz | Problematic for 5G+ |
When to Use Back-Drilling
Required For:
- PCIe Gen4/5 (8-32 GT/s)
- 25G/100G Ethernet
- DDR5 interfaces
- Any signal >10 Gbps
Typically Not Needed:
- USB 2.0 (480 Mbps)
- 1G Ethernet
- Low-speed control signals
- Power distribution vias
Back-Drill Specifications
- Target stub length: 8-10 mils maximum after back-drill
- Drill tolerance: ±3 mils typical, specify on fab drawing
- Back-drill diameter: 8-12 mils larger than original hole
- Cost impact: 10-20% increase, varies by volume
Via-in-Pad Design
Via-in-pad (VIP) places vias directly in component pads, enabling smaller PCB footprints and better thermal/electrical performance. The process requires via filling and planarization (VIPPO: Via-In-Pad Plated Over).
Benefits
- • Enables fine-pitch BGA fanout (<0.5mm)
- • Shorter electrical path = less inductance
- • Better thermal dissipation for power ICs
- • Ideal for bypass cap placement
- • Smaller PCB footprint
Considerations
- • Adds $0.02-0.10 per via
- • Requires filled & planarized vias
- • Must specify fill material (epoxy/copper)
- • Capping over fill required
- • Not all fabs offer this capability
High-Speed Via Design
For signals above 5 Gbps (like PCIe Gen4,USB 3.2,25G Ethernet), via design becomes critical. Apply these advanced techniques:
1. Ground Via Placement
Add 2-4 ground vias within 20 mils of each signal via. For differential pairs, place ground vias between and around the pair. This provides a low-inductance return path and maintainsimpedance through the transition.
2. Anti-Pad Optimization
Increase anti-pad size to raise via impedance closer to 50Ω. Balance with routing density—larger anti-pads block more routing channels on inner layers. Typical range: 25-40 mils diameter.
3. Minimize Transitions
Each layer transition adds ~0.3-0.5 dB of loss. Keep high-speed signals on the same layer pair when possible. If transitions are unavoidable, uselow-loss materials.
4. Differential Via Spacing
For differential pairs, maintain via-to-via spacing equal to trace spacing. Use larger anti-pads to prevent the pads from merging, which would upset the differential impedance.
Manufacturing Considerations
Mechanical Drilling
- • Minimum drill: 8 mils (0.2mm)
- • Standard tolerance: ±2 mils
- • Drill wear affects hole quality
- • Best for through-hole vias
Laser Drilling
- • Minimum: 3-4 mils (75-100µm)
- • Required for microvias
- • UV or CO2 laser types
- • Can't drill through glass fibers
Plating Quality Factors
Via reliability depends on proper copper plating. Key factors include:
- • Plating thickness: 1.0 mil minimum per IPC Class 2
- • Knee coverage at pad-to-barrel junction
- • No voids or cracks in plating
- • Copper crystalline structure quality
Best Practices Checklist
General Via Design
- Match via pad size to drill + 2× annular ring
- Use consistent via sizes per design
- Keep aspect ratio within fab capability
- Remove non-functional pads when possible
High-Speed Signals
- Add ground vias near signal transitions
- Back-drill stubs for >5 Gbps signals
- Minimize layer transitions
- Simulate critical vias in SI tools
Frequently Asked Questions
What is via stub and why does it matter?
A via stub is the unused portion of a through-hole via that extends past the signal layer. At high frequencies (>3 GHz), this stub acts as an antenna, causing resonance and signal reflection. The stub creates a quarter-wave resonance at f = c/(4×L×√εr), where L is stub length. For a 40-mil stub in FR-4, resonance occurs around 9 GHz, significantly degrading signals like PCIe Gen4 or USB 3.2.
When should I use back-drilling?
Use back-drilling when: (1) Signal frequencies exceed 5 GHz, (2) Via stubs are longer than 10 mils, (3) Insertion loss budget is tight, (4) You're designing PCIe Gen4+, 25G Ethernet, or similar high-speed interfaces. Back-drilling typically removes the stub to within 8-10 mils of the signal layer. Cost increase is 10-20% but dramatically improves signal integrity.
How do I calculate via inductance?
Via inductance can be approximated as: L ≈ 5.08h × (ln(4h/d) + 1) nH, where h is via height in inches and d is via diameter. A typical 10-mil via through a 62-mil board has ~1 nH inductance. Reduce inductance by: using larger diameter vias, adding ground vias nearby, using multiple parallel vias for power, or using microvias for shorter paths.
What is via-in-pad and when should I use it?
Via-in-pad places the via directly in the component pad rather than routing to a separate via. Use it for: fine-pitch BGAs (<0.8mm), thermal management (power devices), high-frequency bypass capacitors, and space-constrained designs. The via must be filled and planarized (VIPPO process) to allow proper soldering. This adds ~$0.02-0.05 per via but enables denser designs.
How many ground vias do I need around a signal via?
For optimal signal return path: use at least 2 ground vias per signal via for single-ended signals, 4-6 ground vias for differential pairs. Place ground vias within 20 mils of signal vias for frequencies above 5 GHz. This maintains impedance through the via transition and minimizes inductance. For very high frequencies (>25 GHz), consider via cages or coaxial via structures.