What is Skin Effect?
Skin effect is a fundamental electromagnetic phenomenon where alternating current (AC) tends to flow primarily near the outer surface of a conductor, rather than uniformly throughout its cross-section. At high frequencies, this concentration of current at the "skin" of the conductor effectively reduces the usable conductor area, dramatically increasing AC resistance compared to DC resistance.
Key Insight
At DC (0 Hz), current distributes uniformly through a conductor's cross-section. As frequency increases, current crowds toward the surface due to electromagnetic induction. This is not a material defect or manufacturing issue - it's a fundamental law of physics that affects all conductors.
For modern high-speed digital interfaces like PCIe Gen4/5(8-32 GT/s, with harmonics to 25+ GHz) or 100G Ethernet(56 Gbaud PAM4), skin effect is the dominant source of conductor loss and must be carefully managed through trace geometry, copper quality, and material selection.
Why Skin Effect Matters for PCB Design
- Increased insertion loss: At 10 GHz, a PCB trace can have 10-20× higher resistance than at DC, directly attenuating signal amplitude
- Frequency-dependent behavior: Loss increases with √frequency, making high-frequency components of fast signals suffer more attenuation than lower frequencies
- Eye diagram closure: Excessive loss reduces eye height and width, increasing bit error rate (BER) and potentially requiring retransmission or equalization
- Link budget exhaustion: High-speed protocols have strict insertion loss budgets (e.g., PCIe Gen5 allows ~28 dB at Nyquist). Skin effect can consume half or more of this budget
Understanding skin effect enables you to make informed decisions about trace width, copper weight, surface finish, and material selection to minimize loss and meet your signal integrity requirements.
Physics & Electromagnetic Principles
To properly design for skin effect, it helps to understand the underlying physics. Skin effect arises from electromagnetic induction and Faraday's Law.
The Mechanism
- 1Alternating current creates a time-varying magnetic field: When AC flows through a conductor, it generates a magnetic field that oscillates at the same frequency as the current (Ampère's Law: ∇×H = J).
- 2The magnetic field induces eddy currents: This time-varying magnetic field penetrates the conductor and induces circulating eddy currents within it (Faraday's Law: ∇×E = -∂B/∂t).
- 3Eddy currents oppose the main current: By Lenz's Law, the induced eddy currents create their own magnetic field that opposes the change in the original field. The eddy currents flow in a direction thatopposes the main current in the center of the conductor.
- 4Current crowds to the surface: The opposition is strongest at the center and weakest at the surface. This causes current density to be highest at the conductor surface and decay exponentially toward the center.
Mathematical Description
The current density J as a function of depth x from the surface follows an exponential decay:
// Current density vs depth
J(x) = J₀ · e^(-x/δ)
Where:
J₀ = surface current density
x = depth from surface
δ = skin depth (where J drops to 37% of J₀)
Practical Meaning
About 63% of the total current flows within one skin depth of the surface. 86% flows within two skin depths, and 95% within three skin depths. Beyond 3-4 skin depths, the current is negligible.
This means that once your copper thickness exceeds about 3-4× skin depth, making it thicker provides almost no benefit for AC resistance at that frequency. This is why ultra-thick copper (4 oz, 6 oz) doesn't help for high-speed signals - it only helps for DC current capacity.
Skin Depth Formula & Calculations
The skin depth (δ) is the distance from the conductor surface at which the current density has decreased to 1/e (approximately 37%) of its value at the surface. It quantifies how deeply the AC current penetrates.
General Formula
// Skin depth general formula
δ = √(ρ / (π · f · μ))
Where:
δ = skin depth (meters)
ρ = resistivity of conductor (Ω·m)
f = frequency (Hz)
μ = permeability (H/m) = μᵣ · μ₀
μ₀ = 4π × 10⁻⁷ H/m (permeability of free space)
Simplified Formula for Copper
For copper at 20°C with ρ = 1.68×10⁻⁸ Ω·m and μᵣ = 1 (non-magnetic), the formula simplifies to:
Metric Units
δ(mm) = 66 / √f(MHz)
or
δ(μm) = 66000 / √f(MHz)
Imperial Units
δ(mil) = 2600 / √f(MHz)
or
δ(mil) = 82.2 / √f(GHz)
Example Calculations
Example 1: 1 GHz (PCIe Gen3, 10G Ethernet)
f = 1 GHz = 1000 MHz
δ = 66 / √1000 = 66 / 31.62 = 2.09 μm (0.082 mil)
This is only 6% of 1 oz copper thickness (35 μm)
Example 2: 10 GHz (PCIe Gen5, 25G SerDes)
f = 10 GHz = 10000 MHz
δ = 66 / √10000 = 66 / 100 = 0.66 μm (0.026 mil)
This is only 2% of 1 oz copper - most copper is unused!
Example 3: 28 GHz (56G PAM4, 5G mmWave)
f = 28 GHz = 28000 MHz
δ = 66 / √28000 = 66 / 167.3 = 0.39 μm (0.015 mil)
Comparable to copper grain size - extreme regime!
Temperature Effects
Copper resistivity increases with temperature (~0.4%/°C), which increases skin depth slightly. However, this effect is small compared to frequency variation. For most PCB work at typical operating temperatures (0-85°C), using the 20°C values is sufficient. For extreme environments (>100°C), use:
Skin Effect at Different Frequencies
This comprehensive table shows how skin depth varies with frequency and its practical impact on PCB trace design. Reference: 1 oz copper = 35 μm (1.4 mil) finished thickness.
| Frequency | Skin Depth | vs 1oz Cu | Impact | Typical Uses |
|---|---|---|---|---|
| 100 kHz | 0.21 mm (8.3 mil) | 600% of 1 oz Cu | Negligible - DC resistance dominates | Audio, Power switching |
| 1 MHz | 66 μm (2.6 mil) | 189% of 1 oz Cu | Negligible for PCB traces | Power electronics, EMI |
| 10 MHz | 21 μm (0.83 mil) | 60% of 1 oz Cu | Starts to matter - ~1.5× DC R | High-speed parallel buses |
| 100 MHz | 6.6 μm (0.26 mil) | 19% of 1 oz Cu | Significant - ~3× DC R | Fast Ethernet, USB 2.0 |
| 1 GHz | 2.1 μm (0.08 mil) | 6% of 1 oz Cu | Dominates loss - ~10× DC R | PCIe Gen3, 10G Ethernet |
| 10 GHz | 0.66 μm (0.026 mil) | 2% of 1 oz Cu | Critical + roughness effects | PCIe Gen4/5, 25G+ SerDes |
| 28 GHz | 0.39 μm (0.015 mil) | 1.1% of 1 oz Cu | Extreme - VLP copper required | 56G PAM4, 5G mmWave |
Key Takeaway: The √f Relationship
Notice that skin depth is inversely proportional to the square root of frequency. This means:
- • Doubling frequency reduces skin depth by ~29% (factor of √2 = 1.41)
- • 10× frequency reduces skin depth by ~68% (factor of √10 = 3.16)
- • Going from 1 GHz to 10 GHz reduces skin depth from 2.1 μm to 0.66 μm
Since AC resistance is inversely proportional to the conductive area (which shrinks with skin depth), resistance increases as √f. This is why conductor loss increases roughly linearly with frequency on a dB scale.
Impact on PCB Trace Resistance
As skin depth decreases with frequency, the effective resistance of a PCB trace increases dramatically. This is the primary mechanism of conductor loss in high-speed transmission lines.
AC Resistance vs DC Resistance
For a rectangular trace (typical PCB microstrip or stripline), the DC resistance is:
// DC resistance
R_DC = ρ · L / (W · T)
Where:
ρ = resistivity (1.68×10⁻⁸ Ω·m for copper)
L = trace length (m)
W = trace width (m)
T = trace thickness (m)
At high frequencies where skin effect dominates, the effective thickness becomes limited by skin depth:
// AC resistance (simplified, rectangular trace)
R_AC ≈ ρ · L / (W · δ) for T >> δ
Resistance ratio:
R_AC / R_DC ≈ T / δ (when T > 3δ)
Practical Example: 50Ω Microstrip at 10 GHz
Scenario:
- • Trace: 5 mil wide, 1 oz copper (1.4 mil thick), 2 inch long
- • Substrate: FR-4, εᵣ = 4.3, h = 8 mil
- • Frequency: 10 GHz, skin depth = 0.66 μm = 0.026 mil
DC resistance:
R_DC = 1.68×10⁻⁸ × 0.0508 / (0.000127 × 0.0000356) = 0.19 Ω
AC resistance at 10 GHz:
δ = 0.66 μm, T/δ = 35 μm / 0.66 μm = 53
R_AC ≈ 53 × R_DC = 10 Ω
Result: At 10 GHz, this trace has ~53× higher resistance than at DC! For a 2-inch trace, that's 10Ω of resistance. For a 50Ω transmission line carrying a 1V signal, the voltage drop is significant.
Insertion Loss Calculation
Conductor loss in dB per unit length is commonly expressed as:
// Conductor loss (dB/inch)
Loss = 0.433 × R_AC / Z₀
Where:
R_AC = AC resistance per unit length (Ω/inch)
Z₀ = characteristic impedance (typically 50Ω or 100Ω diff)
0.433 = conversion factor (ln(10)/20)
For our example above (10Ω for 2 inches = 5 Ω/inch):
Loss = 0.433 × 5 / 50 = 0.043 dB/inch
For 10 inches: 0.43 dB total conductor loss at 10 GHz
Why This Matters
High-speed protocols have strict loss budgets. For example:
- • PCIe Gen5 (32 GT/s): Max ~28 dB insertion loss at 16 GHz (Nyquist)
- • USB4 (40 Gbps): Max ~20 dB at 20 GHz
- • 100G Ethernet (56 Gbaud PAM4): Max ~30 dB at 28 GHz
With long traces, connectors, vias, and other discontinuities, every 0.1 dB matters. Minimizing conductor loss through proper design is essential.
Conductor Loss vs Dielectric Loss
Total insertion loss in a PCB trace comes from two main sources: conductor loss (skin effect) and dielectric loss (energy absorbed by the substrate). Understanding both is critical for high-frequency design.
Conductor Loss (R_AC)
Caused by finite conductivity of copper and skin effect pushing current to the surface.
- Frequency dependence: ∝ √f
- Affected by: Trace width, copper thickness (up to ~3δ), surface roughness
- Dominant: Low to mid frequencies (<10 GHz for FR-4)
- Mitigation: Wider traces, smooth copper, shorter routes
Dielectric Loss (tan δ)
Caused by polarization losses in the PCB substrate material (FR-4, Rogers, etc.).
- Frequency dependence: ∝ f (linear)
- Affected by: Material loss tangent (tan δ), dielectric constant (εᵣ)
- Dominant: Very high frequencies (>20 GHz, depends on material)
- Mitigation: Low-loss materials (Megtron, Rogers), thinner dielectric
Dielectric Loss Formula
// Dielectric loss (dB/inch)
α_d = 2.3 × f × √εᵣ × tan(δ) / c
Where:
f = frequency (GHz)
εᵣ = relative permittivity (dielectric constant)
tan(δ) = loss tangent of material
c = speed of light (11.8 inch/ns)
Material Comparison
| Material | εᵣ @ 10 GHz | tan δ @ 10 GHz | Dielectric Loss |
|---|---|---|---|
| Standard FR-4 | 4.3 | 0.020 | High - avoid for >5 GHz |
| Mid-loss FR-4 | 4.2 | 0.012 | Moderate - OK to 10 GHz |
| Megtron 6 | 3.6 | 0.004 | Low - good to 25 GHz |
| Rogers RO4350B | 3.48 | 0.0037 | Low - excellent to 40 GHz |
| Megtron 7 | 3.3 | 0.0025 | Ultra-low - premium choice |
When Does Each Dominate?
For a typical 50Ω microstrip on standard FR-4:
- • Below 1 GHz: Conductor loss dominates (80%+ of total loss)
- • 1-5 GHz: Conductor loss still dominant (60-70%)
- • 5-10 GHz: Both contribute significantly (~50/50)
- • Above 10 GHz: Dielectric loss becomes dominant for standard FR-4
For low-loss materials like Megtron 6 or Rogers, conductor loss remains dominant even at 20+ GHz because dielectric loss is so low. This is why material selection becomes critical at high frequencies.
Surface Roughness Effects
When skin depth becomes comparable to or smaller than the copper surface roughness, current must travel a longer, winding path following the rough surface profile. This roughness-induced loss can increase total conductor loss by 20-40% at frequencies above 10 GHz.
Understanding Copper Roughness
PCB copper foil is not perfectly smooth. It has a rough surface with "teeth" or nodules that improve adhesion to the dielectric material. Roughness is characterized by:
- Rz (peak-to-valley height): The vertical distance from the deepest valley to the highest peak. This is the most common specification for PCB copper (e.g., "Rz = 3 μm").
- Ra (average roughness): The arithmetic mean of surface height deviations. Less commonly specified for PCB work. Typically Ra ≈ Rz/5 to Rz/8.
- Tooth profile: The shape and distribution of roughness - standard ED copper has larger, more pronounced teeth than VLP copper.
Copper Foil Types
| Copper Type | Rz | Loss @ 10 GHz | Applications | Cost |
|---|---|---|---|---|
| Standard ED (STD) | 8-12 μm | Baseline | General purpose, <5 Gbps | Lowest |
| RTF (Reverse Treated) | 4-7 μm | -10% vs STD | 10-25 Gbps | Low |
| Low Profile (LP) | 2-4 μm | -15% vs STD | 25 Gbps, PCIe Gen4 | Moderate |
| VLP (Very Low Profile) | 1-2 μm | -25% vs STD | 56 Gbps PAM4, PCIe Gen5 | High |
| HVLP (Hyper VLP) | <1 μm | -35% vs STD | 112G PAM4, D2D interconnect | Very High |
Hammerstad-Bekkadal Roughness Model
The most commonly used model for roughness-induced loss in PCB design is the Hammerstad-Bekkadal model (1986):
// Hammerstad roughness loss multiplier
K_r = 1 + (2/π) × arctan[1.4 × (Rz/δ)²]
Effective AC resistance:
R_AC_rough = K_r × R_AC_smooth
Where:
Rz = peak-to-valley roughness (same units as δ)
δ = skin depth
Roughness Impact Examples
Standard ED Copper at 10 GHz
Rz = 10 μm, δ = 0.66 μm
Rz/δ = 10/0.66 = 15.15
K_r = 1 + (2/π) × arctan(1.4 × 15.15²) = 1 + 0.637 × arctan(321) ≈ 1.64
Roughness increases loss by 64%!
VLP Copper at 10 GHz
Rz = 1.5 μm, δ = 0.66 μm
Rz/δ = 1.5/0.66 = 2.27
K_r = 1 + (2/π) × arctan(1.4 × 2.27²) = 1 + 0.637 × arctan(7.2) ≈ 1.21
Roughness increases loss by only 21% - much better!
Practical Guidelines
For optimal high-speed performance, target these roughness specifications:
- <5 Gbps: Standard copper (Rz 8-12 μm) is fine
- 5-10 Gbps: RTF or LP copper (Rz 3-6 μm) recommended
- 10-25 Gbps: LP or VLP copper (Rz <3 μm) required
- 25-56 Gbps: VLP copper (Rz <2 μm) mandatory
- >56 Gbps: HVLP copper (Rz <1 μm) essential
Alternative Models
Huray Snowball Model
Developed by Dr. Stephen H. Huray (2010), this model treats roughness as hemispherical "snowballs" on the surface. It requires more detailed roughness characterization (nodule size and density) but is more accurate at very high frequencies (>25 GHz) where Hammerstad can overestimate loss.
The Huray model is available in advanced SI simulation tools like Ansys HFSS and Keysight ADS. Use it when:
- • Working above 25 GHz
- • Your fab can provide detailed roughness characterization
- • Maximum accuracy is needed for ultra-high-speed designs
Copper Weight and Thickness Considerations
Copper weight (e.g., 0.5 oz, 1 oz, 2 oz) specifies the mass of copper per square foot, which translates to thickness. Understanding how copper thickness interacts with skin effect is crucial for proper PCB design.
Copper Weight Specifications
| Weight | Base Thickness | Plated Thickness | Best Use |
|---|---|---|---|
| 0.5 oz | 17.5 μm (0.7 mil) | ~25 μm (1.0 mil) | Fine-pitch traces, thin substrates, HDI |
| 1 oz | 35 μm (1.4 mil) | ~43 μm (1.7 mil) | Standard for most designs, good balance |
| 2 oz | 70 μm (2.8 mil) | ~78 μm (3.1 mil) | High current (power planes, thick traces) |
| 3 oz | 105 μm (4.2 mil) | ~113 μm (4.5 mil) | Heavy power, automotive, industrial |
| 4+ oz | >140 μm (>5.6 mil) | >150 μm (>6 mil) | Very high current, busbars, special apps |
Critical Insight: Thickness vs Frequency
For DC and low-frequency AC (<1 MHz): Thicker copper is better. It directly reduces resistance, voltage drop, and I²R heating. Use the thickest copper your current requirements demand.
For high-frequency AC (>100 MHz): Once copper thickness exceeds ~3× skin depth, additional thickness provides negligible benefit for AC resistance. The current simply doesn't penetrate deep enough to use it.
At 1 GHz: 3δ = 6.3 μm, much less than even 0.5 oz copper (25 μm finished).
At 10 GHz: 3δ = 2.0 μm, less than the roughness of standard copper!
When to Use Each Copper Weight
0.5 oz Copper
- HDI and fine-pitch designs (<4 mil traces)
- Mobile and portable devices
- When using thin core materials (<4 mil)
- High-frequency signals (wider traces OK)
1 oz Copper
- Standard choice for most PCBs
- Good balance of cost and performance
- High-speed digital and mixed-signal
- Moderate current (up to ~5A per trace)
2 oz Copper
- Power distribution (planes and traces)
- High current traces (>10A)
- Mixed designs (2 oz for power, 0.5 oz for signals)
- NOT for high-speed signals (use 0.5-1 oz)
3+ oz Copper
- Very high current (power supplies, motors)
- Automotive, industrial applications
- Thermal management (heat spreading)
- Special fabrication requirements
Mixed Copper Weight Designs
For boards with both high-current power distribution and high-speed signals, consider a mixed copper weight stackup:
- • Outer signal layers: 0.5 oz for fine traces and smooth surface
- • Inner power/ground planes: 2 oz for low DC resistance and current capacity
- • Inner signal layers: 0.5-1 oz depending on routing density
This optimizes for both signal integrity and power delivery, though it increases fabrication cost by 15-30%.
Material Selection for High Frequency
At high frequencies, both conductor loss (skin effect) and dielectric loss matter. Choosing the right PCB laminate material is one of the most impactful decisions for signal integrity in multi-gigabit designs.
Key Material Properties
Dielectric Constant (εᵣ)
Affects impedance and signal velocity. Lower εᵣ means:
- • Faster signal propagation
- • Wider traces for same Z₀
- • Slightly lower dielectric loss
- • Better high-freq performance
Target: 3.0-4.0 @ 10 GHz
Loss Tangent (tan δ)
Measures dielectric loss (energy absorbed). Lower tan δ is critical at high frequencies:
- • Reduces signal attenuation
- • Less frequency-dependent loss
- • Improves eye diagrams
- • Essential for >10 GHz
Target: <0.005 @ 10 GHz
Copper Quality
Surface roughness directly impacts conductor loss via skin effect:
- • VLP/HVLP required for >25 Gbps
- • Specify Rz in fab notes
- • RTF better than standard ED
- • Premium materials often include
Target: Rz <2 μm @ 25+ Gbps
Material Recommendations by Data Rate
1-5 Gbps
Low SpeedExamples: Gigabit Ethernet, USB 2.0, SATA 3.0, SD card, basic SerDes
Material: Standard FR-4 or mid-loss FR-4 is sufficient. Focus on impedance control.
Copper: Standard or RTF copper acceptable.
5-15 Gbps
Medium SpeedExamples: PCIe Gen3,USB 3.1/3.2,10GBASE-KR, SATA Express
Material: Mid-loss FR-4 (tan δ ~0.01) or entry-level low-loss (Isola 370HR, Nelco N4000-13).
Copper: RTF or Low Profile recommended for best margins.
15-32 Gbps
High SpeedExamples: PCIe Gen4/5,25G Ethernet,USB4,DDR5
Material: Low-loss required - Megtron 6, Nelco N4000-13SI, Rogers RO4350B.
Copper: VLP copper mandatory (Rz <2 μm).
32+ Gbps
Ultra High SpeedExamples: 56G PAM4 (PCIe Gen6, 100G/400G Ethernet), 112G PAM4, 800G optics, die-to-die interconnect
Material: Ultra-low-loss only - Megtron 7, Rogers RO3003, advanced PTFE. Verify tan δ <0.003 @ 28 GHz.
Copper: HVLP copper (Rz <1 μm) essential. Special processing required.
External Resources
For detailed material datasheets and selection guides:
Design Guidelines by Frequency Range
This comprehensive reference table provides actionable design guidelines organized by frequency range and typical protocols.
| Frequency | Protocols | Skin Effect | Copper | Material | Key Considerations |
|---|---|---|---|---|---|
| DC - 10 MHz | Power, I²C, SPI, UART | Negligible | Standard ED | Standard FR-4 | DC resistance, current capacity, voltage drop |
| 10-100 MHz | Fast Ethernet, SDRAM, parallel buses | Minor | Standard/RTF | Standard FR-4 | Begin considering skin effect, maintain impedance |
| 100 MHz - 1 GHz | Gigabit Ethernet, USB 2.0, DDR3 | Significant | RTF or LP | Mid-loss FR-4 or better | Skin effect notable, trace width important, loss budgeting |
| 1-10 GHz | PCIe Gen3, USB 3.x, 10G Ethernet, DDR4 | Dominant | LP copper required | Low-loss laminate (Megtron, Nelco) | Roughness begins to matter, loss simulation required |
| 10-30 GHz | PCIe Gen4/5, 25G/50G SerDes, DDR5 | Critical | VLP copper required | Ultra-low-loss (Megtron 6/7, Rogers) | Roughness dominates, VLP mandatory, short traces essential |
| >30 GHz | 56G/112G PAM4, 5G mmWave, 100G+ optical | Extreme | HVLP mandatory | Premium low-loss only | Every detail matters, advanced modeling, tight fab control |
Trace Width Optimization
At high frequencies, wider traces have lower AC resistance because they provide more perimeter for current to flow in the skin. However, wider traces also have lower characteristic impedance.
Strategy: Use the widest trace that maintains your target impedance. For 50Ω microstrip on thin substrates, this might be 3-5 mils. On thicker substrates, you can use 10-20 mil traces while maintaining 50Ω, significantly reducing loss.
Route Length Minimization
Conductor loss is proportional to trace length. At 10 GHz with 0.5 dB/inch loss, a 10-inch trace loses 5 dB - significant for tight link budgets.
Strategy: Place high-speed transceivers close together. Use shortest routing paths. Consider redriving or retiming if distances exceed 8-12 inches for >25 Gbps signals.
Best Practices Checklist
Design Phase
- Calculate skin depth for your highest frequency component
- Select copper weight appropriate for signals (0.5-1 oz) vs power (2+ oz)
- Choose material with suitable tan δ for your frequency range
- Use widest traces compatible with impedance targets
- Model frequency-dependent loss in SI simulations
- Budget for both conductor and dielectric loss
Fabrication Phase
- Specify copper roughness (Rz) for high-speed layers
- Request VLP/HVLP copper for >25 Gbps signals
- Verify fab capability before finalizing design
- Request cross-section analysis to verify copper roughness
- Document material and copper requirements in fab notes
- Consider mixed copper weights for optimal design
High-Speed Specific (>10 Gbps)
Minimize length: Every inch counts. Target <8 inches for 25+ Gbps
Control via stubs:Back-drill for signals >10 Gbps
Use equalization: CTLE/DFE/FFE to compensate for loss
Frequently Asked Questions
What is skin effect and why does it occur?
Skin effect is the tendency of alternating current (AC) to flow primarily near the surface of a conductor, rather than uniformly through its cross-section. It occurs because of electromagnetic induction: the changing current creates a magnetic field that induces eddy currents within the conductor. These eddy currents oppose the main current in the center and reinforce it at the surface, pushing current toward the edges. The higher the frequency, the stronger this effect. This effectively reduces the usable conductor area, increasing AC resistance compared to DC resistance.
How do I calculate skin depth for copper?
Skin depth (δ) for copper is calculated using: δ = √(ρ / πfμ), where ρ is resistivity (1.68×10⁻⁸ Ω·m for copper), f is frequency in Hz, and μ is permeability (μ₀ = 4π×10⁻⁷ H/m for copper). A simplified formula for copper at 20°C is: δ(mm) ≈ 66 / √f(MHz). For example, at 1 GHz: δ = 66/√1000 ≈ 2.1 μm. At 10 GHz: δ ≈ 0.66 μm. This is the depth where current density drops to 37% (1/e) of the surface value.
When does skin effect become significant for PCB design?
Skin effect becomes noticeable above 10 MHz and significant above 100 MHz. For 1 oz copper (35 μm thick), skin depth equals the copper thickness at ~9 MHz. Above this frequency, increasing copper thickness doesn't reduce AC resistance. At 1 GHz, skin depth is only 2.1 μm - just 6% of 1 oz copper thickness - so the AC resistance is roughly 10× the DC resistance. For high-speed digital (>1 Gbps), skin effect is the dominant source of conductor loss and must be carefully managed through trace width optimization and copper surface quality.
Why does copper surface roughness matter at high frequencies?
When skin depth approaches the scale of copper surface roughness (Rz), current must travel a longer path following the rough surface profile rather than a smooth path. Standard electrodeposited (ED) copper has Rz of 8-12 μm with a tooth profile for adhesion. At 10 GHz where skin depth is 0.66 μm, this roughness increases the effective path length by 20-40%, directly increasing loss. The Hammerstad-Bekkadal model quantifies this: loss increases by factor of [1 + (2/π)arctan(1.4(Rz/δ)²)]. Very Low Profile (VLP) copper with Rz <2 μm can reduce loss by 20-30% at 10+ GHz compared to standard copper.
What's the difference between conductor loss and dielectric loss?
Conductor loss (skin effect resistance) is caused by finite conductivity of copper and increases with √frequency due to skin effect. Dielectric loss is caused by energy absorption in the insulating material (PCB substrate) and increases linearly with frequency. At low frequencies (<1 GHz), conductor loss dominates. At very high frequencies (>10 GHz), both contribute significantly. The crossover depends on material: standard FR-4 has high dielectric loss, so conductor loss dominates to ~5 GHz. Low-loss materials like Megtron 6 have lower dielectric loss, so conductor loss dominates to higher frequencies. Total loss is the sum of both.
Does thicker copper help at high frequencies?
Thicker copper helps significantly for DC and low-frequency AC current capacity and voltage drop. However, for high-frequency signals (>100 MHz), once copper thickness exceeds about 3× skin depth, further thickness provides minimal benefit for AC resistance. At 1 GHz, 3δ = 6.3 μm - much less than even 0.5 oz copper (17.5 μm). The benefit of thicker copper at high frequency comes primarily from increased trace width (more perimeter for current), not thickness. Use 0.5-1 oz copper for high-speed signals. Use 2 oz+ only for power/ground planes where DC current capacity matters.
How do I specify low-roughness copper for my PCB?
Include copper roughness requirements in your PCB fabrication notes and stackup specification. For signals >10 Gbps, specify 'Low Profile (LP) or VLP copper on signal layers, Rz <3 μm maximum'. For >25 Gbps, specify 'VLP copper, Rz <2 μm'. Request RTF (reverse-treated foil) instead of standard ED foil. Not all fabricators offer VLP copper, and it increases cost by 10-30%. Verify fab capability before finalizing design. Premium materials like Megtron 6/7 often come with smoother copper as standard. Always request a cross-section analysis to verify roughness in manufactured boards.
What are the Hammerstad and Huray roughness models?
These are mathematical models to predict how copper roughness increases high-frequency loss. The Hammerstad-Bekkadal model (1986) is simpler and uses the roughness parameter Rz (peak-to-valley height): Loss multiplier = 1 + (2/π)arctan(1.4(Rz/δ)²). The Huray model (2010) is more accurate and models roughness as spherical nodules on the surface. It requires more detailed roughness characterization but better predicts loss at very high frequencies. Most PCB design tools use Hammerstad for simplicity. For designs >25 GHz, consider Huray model with roughness data from your fabricator.