What is Impedance Matching and Why It Matters
Impedance matching is the practice of designing electrical networks so that the impedance of a source, transmission line, and load are equal (or properly terminated) to maximize power transfer and minimize signal reflections. When impedances are mismatched, part of the signal reflects back toward the source, causing:
- Signal reflections: Ringing, overshoot, and undershoot that degrade signal quality
- Reduced noise margins: Makes the system more susceptible to noise and errors
- EMI emissions: Uncontrolled reflections radiate electromagnetic interference
- Timing errors: Reflections cause false triggering and timing violations
- Power loss: In RF systems, reflected power can damage amplifiers
Key Insight
At frequencies where the trace length exceeds about λ/10 (one-tenth wavelength), the PCB trace must be treated as atransmission line rather than a simple wire. For a typical FR-4 board, this critical length is approximately 2.5 inches at 500 MHz, 1 inch at 1 GHz, and just 0.25 inches at 5 GHz. Modern interfaces like PCIe Gen4 (16 GT/s) andUSB4 (40 Gbps) require careful impedance control and termination.
The Maximum Power Transfer Theorem
In RF and analog circuits, maximum power is transferred from source to load when the load impedance equals the complex conjugate of the source impedance. In digital systems with real impedances, maximum power transfer (and minimum reflection) occurs when:
Z_source = Z_0 = Z_load
Where Z_0 is the characteristic impedance of the transmission line (typically 50Ω for RF, 50-75Ω for coax, 40-90Ω for digital, 85-100Ω for differential pairs).
Transmission Line Theory Basics
A transmission line is any pair of conductors that can carry an electromagnetic signal from one point to another. On a PCB, this includes microstrip,stripline, anddifferential pairs.
Characteristic Impedance (Z_0)
The characteristic impedance Z_0 is the ratio of voltage to current for a wave traveling down an infinitely long transmission line. It depends on the geometry and dielectric properties:
// General form
Z_0 = √(L / C)
// For microstrip (approximation)
Z_0 ≈ (87 / √(εr + 1.41)) × ln(5.98h / (0.8w + t))
// For stripline
Z_0 ≈ (60 / √εr) × ln(4b / (0.67π(t + 0.8w)))
Where L is inductance per unit length, C is capacitance per unit length, εr is dielectric constant, w is trace width, h is dielectric height, t is copper thickness, and b is distance between planes. Use ourimpedance calculator for precise values.
Propagation Velocity and Delay
Signals travel along a PCB trace at a velocity slower than the speed of light in vacuum due to the dielectric material:
v_p = c / √εr_eff
// For FR-4 (εr ≈ 4.3): v_p ≈ 144 ps/inch
// For Rogers 4350B (εr ≈ 3.48): v_p ≈ 125 ps/inch
This propagation delay is critical fortiming analysis and length matching in high-speed differential pairs.
When to Treat a Trace as a Transmission Line
Use transmission line analysis when the trace length L exceeds:
L > t_rise × v_p / 6
For a 1 ns rise time signal on FR-4: L > 1 ns × 144 mm/ns / 6 ≈ 24 mm (1 inch). Faster signals with sub-nanosecond edges require transmission line treatment for even shorter traces.
Reflections and VSWR
When a signal encounters an impedance discontinuity, part of it reflects back toward the source. The amount of reflection is quantified by the reflection coefficient (Γ):
Key Formulas
Understanding VSWR
VSWR measures the severity of standing waves created by reflections. Common values and their meanings:
| VSWR | Return Loss | Reflected Power | Quality |
|---|---|---|---|
| 1.0:1 | ∞ dB | 0% | Perfect match (theoretical) |
| 1.2:1 | 20.8 dB | 0.8% | Excellent |
| 1.5:1 | 14.0 dB | 4% | Good (typical spec) |
| 2.0:1 | 9.5 dB | 11% | Acceptable (marginal) |
| 3.0:1 | 6.0 dB | 25% | Poor (may damage PA) |
Critical for Power Amplifiers
In RF transmitters and power amplifiers, high VSWR (>2:1) can cause reflected power to damage the output stage. Always verify antenna or load impedance before applying full power. Many modern transmitters include automatic shutdown protection when VSWR exceeds safe limits.
Termination Strategies
Termination absorbs the signal energy at the end of a transmission line, preventing reflections. Different termination schemes are optimized for different applications based on power consumption, topology, and signal characteristics.
Series Termination (Source)
At driver/sourceAdvantages
- Low power consumption
- Simple single resistor
- No DC load
- Excellent for point-to-point
Disadvantages
- Not for multi-drop
- Half-voltage at stub points
- Requires low-impedance driver
Best For
Clock signals, address/data buses, single-ended point-to-point
Parallel Termination (Load)
At receiver/loadAdvantages
- Works with multi-drop
- Full signal swing everywhere
- Simple to implement
Disadvantages
- High DC current
- Increased power
- Static load on driver
Best For
Multi-drop buses, backplanes, slow clock distribution
Thevenin Termination
At loadAdvantages
- Matches Z_0 precisely
- Works for multi-drop
- Biases to logic threshold
Disadvantages
- Highest power consumption
- Requires two resistors
- DC current flow
Best For
Legacy buses, TTL/CMOS interfaces, precision matching
AC Termination
At loadAdvantages
- No DC power consumption
- Good for static signals
- Capacitor blocks DC
Disadvantages
- Not for high-frequency AC
- Cap must be chosen carefully
- Response time limited
Best For
Address lines, control signals, static or slow-changing signals
On-Die Termination (ODT)
Inside ICAdvantages
- No external components
- Configurable impedance
- Space saving
- Dynamic control
Disadvantages
- Limited to supported ICs
- Thermal constraints
- Fixed options only
Best For
DDR memory, modern CPUs, high-speed SerDes
Choosing the Right Termination
- Point-to-point, low power: Series termination
- Multi-drop bus: Parallel or Thevenin termination
- Static/slow signals: AC termination
- Modern high-speed (DDR, PCIe): On-die termination (ODT)
Source Termination vs Load Termination
Source Termination
A series resistor R_s is placed at the driver output. The resistor value is chosen so that R_s + Z_driver = Z_0. For a low-impedance driver (Z_driver ≈ 0), use R_s = Z_0.
How It Works:
- Driver sends signal at half amplitude (voltage divider)
- Signal propagates down line at half voltage
- At load (high impedance), signal doubles to full swing
- Reflection returns but is absorbed by R_s + Z_driver
Best for: Clock lines, SPI, I2C, single-ended point-to-point where power efficiency is critical
Load Termination
A resistor R_L = Z_0 is placed at the receiver, typically to VCC (pull-up) or GND (pull-down), or both (Thevenin). The termination absorbs the incident wave.
How It Works:
- Driver sends signal at full amplitude
- Signal propagates at full voltage
- At load, R_L absorbs incident wave (no reflection)
- Continuous DC current flows through R_L
Best for: Multi-drop buses, backplanes, legacy parallel interfaces where multiple receivers tap the line
Power Consumption Comparison
For a 50Ω line driven at 3.3V:
- Series termination: P ≈ 0 W (no DC path)
- Parallel termination (to GND): P = 3.3² / 50 = 218 mW per line (high state)
- Thevenin termination: P = constant DC current regardless of logic state
For high-speed interfaces with many signals (e.g., DDR with 72+ lines), power consumption is a critical design constraint. This is why modern designs use ODT which can be dynamically enabled only during transitions.
Differential Termination Techniques
Differential signals (used inUSB,PCIe,Ethernet,HDMI, LVDS) carry information in the voltage difference between two complementary signals. Proper termination maintains signal integrity and common-mode rejection.
Differential Termination Resistor
Place a resistor equal to the differential impedance (Z_diff) across the positive and negative lines at the receiver end:
R_diff = Z_diff (typically 85-100Ω)
// Common values:
USB: 90Ω ± 15%
PCIe: 85Ω ± 15%
LVDS: 100Ω ± 5%
Ethernet 10/100: 100Ω
Correct: Differential Termination
Single resistor between P and N lines at receiver:
Signal_P ----/\/\/\---- Signal_N
R = Z_diff (e.g., 100Ω)
- ✓ Maintains differential impedance
- ✓ Preserves common-mode rejection
- ✓ Low power consumption
Wrong: Single-Ended Termination
Never terminate each line to ground separately:
Signal_P ----/\/\/\---- GND
Signal_N ----/\/\/\---- GND
- ✗ Destroys differential impedance
- ✗ Degrades common-mode rejection
- ✗ Doubles power consumption
Common-Mode Termination
Some interfaces (like Ethernet) use additional common-mode termination to filter noise. This consists of two resistors (typically 49.9Ω each) from each line to a center tap:
Signal_P ----/\/\/\----+----/\/\/\---- Signal_N
49.9Ω | 49.9Ω
|
Center Tap (may connect to cap or bias)
This configuration provides both differential termination (49.9Ω + 49.9Ω = 100Ω differential) and a path for common-mode noise to ground through the center tap capacitor.
Impedance Discontinuities and How to Handle Them
An impedance discontinuity is any abrupt change in characteristic impedance along a signal path. Common sources include:
1. Via Transitions
Vias have lower impedance (25-35Ω) than typical traces (50Ω) due to their geometry. Via stubs create resonances.
Solution: Back-drill stubs, add ground vias nearby, use smaller via diameter, increase anti-pad size.
2. Trace Width Changes
Abrupt width changes create impedance steps that reflect signals. Common at component pads or layer transitions.
Solution: Taper width changes over 3× the width change distance. Keep narrow sections < λ/20. Use teardrop pads for smooth transitions.
3. Connectors and Cables
Most connectors have different impedance than PCB traces. Poor contacts add resistance and inductance.
Solution: Use controlled-impedance connectors (e.g., high-speed Samtec, Molex). Keep connector pins short. For cables, use matched-impedance coax or twinax.
4. Stubs and T-Junctions
Unterminated stubs create reflections at their resonant frequencies. Common in multi-drop topologies.
Solution: Keep stub length < λ/20 at highest frequency. For DDR, use fly-by topology instead of T-branches. Terminate unused stubs with Z_0 or remove them.
5. Layer Changes
Changing from microstrip to stripline (or vice versa) changes dielectric environment and impedance.
Solution: Adjust trace width at layer transition to maintain constant Z_0. Useimpedance calculator for both geometries. Add ground vias at transition.
Rule of Thumb: λ/20 Criterion
A discontinuity can be ignored if its physical length is less than λ/20 at the highest frequency of interest. For a 10 GHz signal in FR-4 (λ ≈ 15 mm), this means discontinuities shorter than 0.75 mm have minimal impact. At 25 GHz (PCIe Gen5, 25G Ethernet), λ/20 ≈ 0.3 mm—every detail matters.
When Termination is Not Needed
Not every signal requires termination. Adding unnecessary termination wastes power and board space. Skip termination when:
Safe to Skip Termination
- Very short traces: L < t_rise × v_p / 6 (electrically short)
- Slow signals: Rise time > 5 ns, frequency < 10 MHz
- Open-drain/open-collector: External pull-up provides DC path
- High receiver input impedance: Input Z > 10× Z_0 (minimal loading)
- Internal termination: Modern ICs (CPUs, FPGAs) have built-in termination
Must Use Termination
- High-speed serial: USB 3+, PCIe, SATA, Ethernet > 100 Mbps
- Fast clocks: > 50 MHz, especially with multiple loads
- Memory buses: DDR3/4/5, QPI, HyperBus
- Long traces: > 6 inches at 100+ MHz
- Backplanes and cables: Always control impedance
Quick Decision Guide
if (trace_length > rise_time × velocity / 6) then
use_termination = true
else
use_termination = false
end
For modern designs with sub-nanosecond edges, this often means termination is required for traces longer than 1-2 inches.
Interface-Specific Requirements
Different high-speed interfaces have specific impedance and termination requirements defined by their standards. Here is a comprehensive reference:
| Interface | Speed | Impedance | Termination | Notes |
|---|---|---|---|---|
| USB 2.0 | 480 Mbps | 90Ω differential | Internal 45Ω to 3.3V (in transceiver) | Series termination on data lines |
| USB 3.x/4 | 5-40 Gbps | 85-95Ω differential | Internal 45-50Ω | AC coupling caps required, strict length matching |
| PCIe Gen3 | 8 GT/s | 85Ω differential ±15% | Internal 50Ω differential | AC coupling, back-drill vias, length matching ±5 mil |
| PCIe Gen4/5 | 16-32 GT/s | 85Ω differential ±10% | Internal ODT | Low-loss materials, back-drilling mandatory, skew <1 ps |
| DDR4 | 3200 MT/s | 40Ω single-ended | ODT 40-120Ω programmable | Fly-by topology, on-die termination at DRAM and controller |
| DDR5 | 6400 MT/s | 40Ω single-ended | ODT with per-rank control | Point-to-point topology, decision feedback equalization |
| 1G Ethernet (SGMII) | 1.25 Gbps | 100Ω differential | Internal (PHY) | AC coupling, 100Ω differential pairs |
| 10G/25G Ethernet | 10-25 Gbps | 85-100Ω differential | Internal 50Ω per side | Back-drilling for >10G, low-loss PCB materials |
USB Design Notes
USB 2.0 (480 Mbps) uses 90Ω differential impedance with internal 45Ω termination to 3.3V in the transceiver. USB 3.x/4 (5-40 Gbps) requires AC coupling capacitors (typically 100-200 nF) and strict length matching (<2 mil intra-pair skew).
View USB design example →PCIe Design Notes
PCIe uses 85Ω differential (±15% Gen3, ±10% Gen4+) with internal ODT. Gen4/5 requires back-drilling of vias, low-loss PCB materials (Dk < 4.0, Df < 0.005), and careful impedance control. Skew must be <1 ps for Gen5.
View PCIe design example →DDR Memory Design Notes
DDR uses 40Ω single-ended impedance with programmable on-die termination (ODT) at both controller and DRAM. DDR4 uses fly-by topology with termination at end of daisy chain. DDR5 uses point-to-point with improved signal integrity.
View DDR design example →Ethernet Design Notes
Ethernet uses 100Ω differential pairs with magnetics for isolation. 1000BASE-T uses hybrid termination, while 10GBASE-KR uses internal termination. 25G+ requires controlled impedance connectors and back-drilled vias.
View Ethernet design example →Simulation and Verification
For high-speed designs (>1 Gbps), simulation is essential to verify impedance matching and signal integrity before fabrication. Modern EDA tools provide comprehensive analysis capabilities.
Pre-Layout Simulation
- • IBIS model validation (driver/receiver)
- • Topology analysis (point-to-point vs multi-drop)
- • Termination scheme selection
- • Initial impedance targets
- • Eye diagram requirements
Tools: HyperLynx, Mentor PADS, Cadence Sigrity
Post-Layout Simulation
- • Extract parasitics (vias, traces, planes)
- • TDR (Time Domain Reflectometry) analysis
- • Eye diagram with actual routing
- • Crosstalk coupling analysis
- • Return loss / VSWR across frequency
Tools: Ansys HFSS, CST, Keysight ADS, Polar SI9000
Key Simulation Checks
1. TDR (Time Domain Reflectometry)
Simulates sending a step function down the trace and observing reflections. Ideal for identifying impedance discontinuities (vias, connectors, width changes). A flat TDR trace at Z_0 indicates good impedance control.
2. Eye Diagram Analysis
Superimposes many bit transitions to visualize jitter, overshoot, and noise margins. A wide-open eye indicates good signal integrity. Measure eye height and width against spec requirements (e.g., PCIe requires specific eye mask).
3. S-Parameter Extraction
Characterizes insertion loss (S21) and return loss (S11) across frequency. Critical for multi-gigabit SerDes. S21 > -6 dB and S11 < -10 dB at Nyquist frequency are typical requirements.
Measurement After Fabrication
Always verify critical signals with lab instruments:
- TDR measurement with oscilloscope
- VNA (Vector Network Analyzer) for S-parameters
- High-speed oscilloscope for eye diagrams
- Spectrum analyzer for EMI compliance
Best Practices Checklist
General Design Rules
- Calculate critical trace length: L_crit = t_rise × v_p / 6
- Use impedance calculator for all high-speed traces
- Specify impedance tolerance in fab notes (±10% typical)
- Place termination resistors physically close to load/source
- Use 1% tolerance resistors for critical terminations
High-Speed Specific
- Back-drill vias for signals > 5 Gbps
- Match differential pair lengths to < 5 mils intra-pair
- Use AC coupling caps for DC-balanced protocols (PCIe, SATA)
- Simulate with IBIS models before layout finalization
- Add test points for TDR measurement on prototypes
Differential Signals
- Terminate across pair, never to ground separately
- Route pairs symmetrically with same layer transitions
- Maintain constant spacing for impedance control
- Avoid crosstalk with 3× spacing to adjacent pairs
Common Mistakes to Avoid
- Never use series termination on multi-drop buses
- Do not terminate differential pairs to ground individually
- Avoid stubs longer than λ/20 at max frequency
- Never assume 50Ω without calculation/measurement
Frequently Asked Questions
What is impedance matching and why does it matter?
Impedance matching ensures the source impedance, transmission line impedance (Z_0), and load impedance are equal or properly terminated. When impedances match, maximum power transfers from source to load and signal reflections are minimized. Mismatches cause reflections that create ringing, overshoot, EMI, and reduced noise margins. For high-speed digital (>100 MHz), reflections degrade eye diagrams and increase bit error rates. Proper matching is critical for USB, PCIe, DDR, Ethernet, and RF systems.
What is the difference between source and load termination?
Source termination places a series resistor at the driver, creating a voltage divider that absorbs reflections returning from the load. The signal is half-amplitude during propagation but reaches full swing at the load. Load termination places a resistor at the receiver matching the line impedance, absorbing the incident wave. Source termination uses less power and works for point-to-point, while load termination works for multi-drop buses but consumes DC power.
When should I use series vs parallel termination?
Use series (source) termination for point-to-point signals with one driver and one receiver (e.g., clock lines, SPI, I2C at moderate speeds). It uses minimal power and no DC current. Use parallel (load) termination for multi-drop topologies where multiple receivers tap the line (e.g., address buses, multi-drop LVDS). Parallel termination provides full signal swing everywhere but draws continuous current. For DDR and modern high-speed interfaces, use on-die termination (ODT) which combines benefits of both.
What is VSWR and what values are acceptable?
VSWR (Voltage Standing Wave Ratio) measures impedance mismatch as the ratio of maximum to minimum voltage along a transmission line. VSWR = (1 + |Γ|) / (1 - |Γ|), where Γ is reflection coefficient. VSWR = 1:1 is perfect (no reflection). VSWR < 1.5:1 (return loss > 14 dB) is acceptable for most applications. VSWR < 1.2:1 (RL > 20 dB) is excellent. For power amplifiers, VSWR > 2:1 can damage the output stage. Digital interfaces typically specify return loss > 10 dB at Nyquist frequency.
How do I choose termination for differential signals?
For differential signals (USB, PCIe, Ethernet, LVDS), use differential termination equal to the differential impedance (typically 85-100Ω) across the pair, not to ground. Place the resistor physically close to the receiver to minimize stub length. For very high-speed (>10 Gbps), use internal termination in transceivers to eliminate board-level parasitics. Never use single-ended termination on differential pairs—it breaks common-mode balance and degrades noise immunity.
What are impedance discontinuities and how do I fix them?
Impedance discontinuities are abrupt changes in characteristic impedance along a signal path (e.g., vias, connectors, trace width changes, stubs). Each discontinuity reflects part of the signal. Fix discontinuities by: (1) minimizing via stubs with back-drilling, (2) using controlled-impedance connectors, (3) tapering trace width changes over >3× width change, (4) keeping stub lengths <λ/20 at highest frequency, (5) adding ground vias near signal vias. For 10+ Gbps, every discontinuity must be optimized and simulated.