Design PCIe Gen3, Gen4, and Gen5 interfaces. Learn differential routing, via optimization, and material selection for the highest-bandwidth PCB interconnects.
| Generation | Data Rate | Bandwidth | Impedance | Material | Encoding |
|---|---|---|---|---|---|
| PCIe 3.0 | 8 GT/s | 1 GB/s/lane | 85Ω | FR-4/Mid-loss | 128b/130b |
| PCIe 4.0 | 16 GT/s | 2 GB/s/lane | 85Ω | Mid-loss | 128b/130b |
| PCIe 5.0 | 32 GT/s | 4 GB/s/lane | 85Ω | Low-loss | 128b/130b |
| PCIe 6.0 | 64 GT/s | 8 GB/s/lane | 85Ω | Ultra low-loss | PAM4 |
PCIe requires 85Ω ±15% differential impedance for all generations. This translates to ~42.5Ω single-ended. The tighter the tolerance, the better - aim for ±10% for Gen4 and ±7% for Gen5. Work with your fab to achieve consistent impedance across the board.
PCIe slots have specific pinouts with TX/RX lanes, power, and sideband signals. Route each differential pair with consistent impedance. Keep TX and RX pairs separated to avoid crosstalk. Use via optimization at layer transitions. Edge-finger impedance matching is critical for add-in cards.
PCIe Gen5 at 32 GT/s requires low-loss materials like Megtron 6 or similar (Df < 0.004). Standard FR-4 has too much loss. For Gen4, mid-loss materials (Df ~0.008-0.010) often work. Always run channel simulation to verify your loss budget before finalizing material selection.