Master HDMI 1.4, 2.0, and 2.1 interface design. Learn TMDS/FRL routing, connector layout, and signal integrity for 4K/8K video applications.
| Version | Bandwidth | Max Resolution | Data Lanes | Per-Lane Rate | Impedance |
|---|---|---|---|---|---|
| HDMI 1.4 | 10.2 Gbps | 4K@30Hz | 3 TMDS | 3.4 Gbps/lane | 100Ω diff |
| HDMI 2.0 | 18 Gbps | 4K@60Hz | 3 TMDS | 6 Gbps/lane | 100Ω diff |
| HDMI 2.1 | 48 Gbps | 8K@60Hz | 4 FRL | 12 Gbps/lane | 100Ω diff |
TMDS (Transition Minimized Differential Signaling) uses 3 data lanes plus 1 clock lane. Each lane is a differential pair requiring 100Ω impedance. Route pairs with tight coupling, match lengths within pairs to ±5 mils, and keep all lanes similar length. The clock lane should be slightly shorter than data lanes.
HDMI 2.1 introduces FRL (Fixed Rate Link) signaling at up to 12 Gbps per lane. It uses 4 differential pairs for data (no separate clock). The higher speeds require lower-loss PCB materials, tighter impedance control, and careful via optimization. Consider using a retimer IC for long traces.
Place TVS diode arrays close to the HDMI connector. Use low-capacitance ESD devices (<0.5pF) to avoid signal degradation. Common mode chokes help with EMI. Route ESD devices inline with minimal stub length. The 5V and HPD pins need robust protection as they face direct user contact.