Master DDR4 and DDR5 memory interface design. Learn fly-by topology, timing constraints, impedance requirements, and layout techniques for reliable memory systems.
| Type | Speed | Voltage | DQ Impedance | CLK Impedance | Topology |
|---|---|---|---|---|---|
| DDR4-2400 | 2400 MT/s | 1.2V | 40Ω | 40Ω | Fly-by |
| DDR4-3200 | 3200 MT/s | 1.2V | 40Ω | 40Ω | Fly-by |
| DDR5-4800 | 4800 MT/s | 1.1V | 40Ω | 40Ω | Fly-by |
| DDR5-6400 | 6400 MT/s | 1.1V | 40Ω | 40Ω | Fly-by |
| LPDDR5 | 6400 MT/s | 1.05V | 40Ω | 40Ω | Point-to-point |
Fly-by topology routes clock, command, and address signals sequentially from the controller to each DRAM chip. This creates intentional skew that is compensated during training. It improves signal integrity by reducing stub lengths and reflections compared to T-branch topology used in older DDR generations.
DDR data signals are byte-lane based - each DQ byte (8 bits) routes to specific pins on the DRAM. Match DQ lengths within each byte lane (±25 mils for DDR4). DQ signals are point-to-point. Use 40Ω single-ended impedance. Route DQ on inner layers for better isolation from CMD/ADDR.
Write leveling is a training procedure that compensates for fly-by skew. The controller sends DQS and the DRAM compares DQS arrival to the clock. The controller adjusts DQS timing to each DRAM independently. This allows fly-by topology to work despite intentional clock skew between DRAMs.