Design 100Ω differential pairs for USB, HDMI, Ethernet, and PCIe. Calculate odd-mode impedance, coupling factor, and optimize trace geometry for high-speed serial interfaces.
Edge-Coupled Differential Microstrip
Understanding the relationship between single-ended, odd-mode, and differential impedance
Impedance of each trace when the other is grounded (no coupling)
Impedance of each trace when driven differentially (P+, N-)
Total impedance between P and N traces (the spec everyone uses)
k = coupling coefficient (0 to 1)
Zdiff ≈ 2 × Z₀ when k → 0 (loose coupling)
| Interface | Zdiff Target | Data Rate | Notes |
|---|---|---|---|
| USB 2.0 | 90Ω ±15% | 480 Mbps | Often relaxed to 90Ω |
| USB 3.0/3.1 | 90Ω ±10% | 5/10 Gbps | TX and RX pairs |
| USB4 / TB3 | 85Ω ±10% | 40 Gbps | Very tight skew |
| HDMI 1.4/2.0 | 100Ω ±15% | 10.2/18 Gbps | 4 TMDS pairs |
| DisplayPort | 100Ω ±10% | 32.4 Gbps | HBR3 |
| PCIe Gen3 | 85Ω ±15% | 8 GT/s | Per lane |
| PCIe Gen4/5 | 85Ω ±10% | 16/32 GT/s | Tight tolerance |
| 1G Ethernet | 100Ω ±10% | 1 Gbps | Cat5e compatible |
| 10G/25G Ethernet | 100Ω ±10% | 10/25 Gbps | SFP+ / SFP28 |
| SATA III | 100Ω ±10% | 6 Gbps | TX and RX |
| DDR4/DDR5 | 80Ω ±10% | Variable | DQ, DQS pairs |
| LVDS | 100Ω ±10% | 655 Mbps | Display panels |
Match P and N trace lengths within each pair:
Maintain constant S (gap) along entire length:
Continuous ground plane is critical:
Optimize coupling for best performance:
Minimize impedance discontinuity at vias:
Design for TDR verification:
Most common for USB, HDMI, Ethernet, PCIe
Used in dense BGA breakout, flex circuits
Z₀ is the single-ended characteristic impedance. Zodd (odd-mode impedance) is the impedance seen by each trace when driven differentially. Zdiff (differential impedance) = 2 × Zodd. Due to mutual coupling, Zodd < Z₀, typically Zodd ≈ 0.7 × Z₀ for tightly coupled pairs, making Zdiff ≈ 1.4 × Z₀.
100Ω differential became the standard because it's easily achievable with common PCB geometries and works well with differential driver ICs. Most high-speed interfaces (USB, HDMI, DisplayPort, Ethernet, PCIe) specify 100Ω ±10%. Some legacy interfaces use 90Ω (LVDS) or 85Ω.
Edge-coupled pairs run side-by-side on the same layer, coupled through the gap between them. Broadside-coupled pairs are stacked vertically on adjacent layers. Edge-coupled is more common and easier to route; broadside is used when horizontal space is limited but requires more precise layer registration.
Tighter spacing (smaller S/W ratio) increases coupling and reduces Zdiff. For 100Ω targets, S ≈ W is common (1:1 ratio). Too tight (S < W) may cause manufacturing issues and excessive coupling. Too loose (S > 3W) provides minimal differential benefit. The 3W rule for isolation doesn't apply to intentional differential pairs.
Differential signaling significantly reduces EMI because the fields from P and N traces partially cancel. However, this only works if the pair is symmetric (equal length, spacing, and timing). Skew between P and N converts differential signal to common-mode, which radiates. Keep skew < 5% of rise time.
Single-ended impedance as baseline for differential design.
Shielded inner layer traces for noise-sensitive differential pairs.
CPW/GCPW for RF differential pairs at mmWave frequencies.
Complete reference of impedance equations including Zdiff.
Differential via pairs and back-drilling techniques.
NEXT/FEXT between differential pairs and isolation rules.
Termination techniques for differential interfaces.
Complete A-Z reference of PCB and SI terms.